Embodiments of the present invention relate to removing resist from a substrate while controlling properties of underlying features being etched on the substrate.
In substrate fabrication processes, semiconductor, dielectric and conductor materials are formed on a substrate and etched to form patterns of gates, vias, contact holes and interconnect features. These materials are typically formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), oxidation and nitridation processes. For example, in CVD processes, a reactive gas is used to deposit a layer of material on the substrate, and in PVD processes, a target is sputtered to deposit material on the substrate. In oxidation and nitridation processes, a layer of oxide or nitride, typically silicon dioxide or silicon nitride, respectively, is formed by exposing the substrate to a suitable gaseous environment. In etching processes, a patterned etch-resistant mask of photoresist and/or a hard mask is formed on the substrate by photolithographic methods, and the exposed portions of the substrate are etched by an energized gas.
The dielectric layers on a substrate are etched in dielectric etching processes to form vias for contact holes. In the etching process, a resist layer is deposited over the dielectric layer and patterned by lithography to expose portions of the underlying dielectric material. Thereafter, the exposed portions of the dielectric layer are etched to form features on the substrate. After the etching process, residual resist remaining above the features is removed from the substrate in a process commonly known as resist stripping.
However, it is difficult to strip the overlying remnant resist without damaging the underlying dielectric features especially when both the resist and the underlying material contains the same element. Conventional resist stripping processes that remove the remnant photoresist which contains carbon by ashing the carbon in the resist in an energized plasma of oxygen, or oxygen and ammonia, damage the underlying etched features comprising a low k dielectric which also contains carbon. Conventional resist stripping plasma chemistries remove excessive amounts of this carbon from the underlying features, causing carbon depletion and increased porosity, which in turn undesirably increases the dielectric constant of the material. Further, the sidewalls can also be etched horizontally to provide narrower features of varying cross-section and undesirable wine-glass shaped profiles. It is desirable to maintain consistent critical dimensions and shapes for the etched dielectric features.
Another problem arises when attempting to control the edge facet height of the underlying low k dielectric features. This edge facet height is important because it controls the coverage of the copper barrier or seed layer coverage in subsequently conducted metal deposition processes. The desirable amount of edge facet is usually decided by integration. In conventional resist stripping processes, the edges and corners of the underlying dielectric features are often not sufficiently etched back to provide an undesirable cross-sectional profile of the dielectric feature that prevents subsequent uniform copper barrier or seed deposition into the hollow space between the dielectric features.
Therefore, it is desirable to be able to remove the remnant resist overlying etched dielectric features without damaging underlying etched dielectric features. It is further desirable to maintain good critical dimension control of these features. It is also desirable to control the edge facet height of the dielectric features.